1. Field of the Invention
This invention relates generally to power-on reset circuits and more specifically to a power supply voltage level sensing circuit which, when coupled with a power-on reset circuit, creates a voltage sensing power-on reset circuit which generates a reset signal not only when the power supply voltage is first applied to the circuit, but also when the power supply voltage level falls below a selected value.
2. Description of Prior Art
Integrated circuits typically contain bistable components such as registers, flip-flops, latches and memory elements. When the power supply voltage is applied to a circuit containing such components, the initial state of the components, and hence the circuit, depends upon the rise time of the power supply voltage and the threshold voltages of the transistors comprising the components. Accordingly, most integrated circuits include a power-on reset circuit to initialize the various components when power is first applied to the circuit.
Some circuit components, such as logic elements and flip-flops, require a certain amount of time to reach a stable operating condition after receipt of a reset signal. Thus, the power-on reset circuit maintains an output signal at a first level for a period of time sufficient to allow the circuit components to stabilize and then the output signal is switched to a second level, complementary to the first level, and maintained at the second level for as long as power is applied to the circuit.
FIG. 1 shows a prior art CMOS power-on reset circuit 100. The power-on reset circuit 100 is compatible with integrated circuits having a wide range of power supply voltage rise times Power-on reset circuit 100 includes initializing buffer 100-5, delay circuit 100-1, and discharge circuit 100-2 Initializing buffer 100-5 includes input (secondary) inverter 100-3 and initializing circuit 100-4.
Initializing circuit 100-4 includes the P-channel enhancement mode transistor P2 and initializing inverters 40, 50. Inverter 40 comprises an unimplanted P channel enhancement mode transistor PLT2 and an N channel enhancement mode transistor N5. Similarly, inverter 50 comprises P channel enhancement mode transistor P3 and N channel enhancement mode transistor N6.
The drain 18 and source 33 of transistor P2 are connected to the positive power supply voltage V.sub.CC and the gate 19 of transistor P2 is connected to node lB. Gates 20 and 21 of transistors PLT2 and N5, respectively, are also connected to node 1B. Source 22 of transistor PLT2 and source 28 of transistor P3 are connected to the power supply voltage V.sub.CC and source 25 of transistor N5 and source 31 of transistor N6 are connected to ground. Drains 23 and 24 of transistors PLT2 and N5, respectively, are connected to node 1C. Gates 26 and 27 of transistors P3 and N6, respectively, are also connected to node 1C. Drains 29 and 30 of transistors P3 and N6, respectively, are connected to output node 1D.
Input (secondary) inverter 100-3 comprises unimplanted P channel enhancement mode transistor PLT1 and N channel enhancement mode transistor N4. Gates 12 and 13 of transistors PLT1 and N4, respectively, are connected to node 1A, and drains 15 and 16 of transistors PLT1 and N4, respectively, are connected to node 1B. Source 14 of transistor PLT1 is connected to power supply voltage V.sub.CC and source 17 of transistor N4 is connected to ground.
Delay circuit 100-1 includes N channel enhancement mode transistor N1 and P channel enhancement mode transistor P1. Gate 2 and drain 1 of transistor N1 are connected to V.sub.CC and source 3 of transistor N1 is connected to the source 4 of transistor P1. Gate 5 of transistor P1 is connected to ground and drain 6 of transistor P1 and gate 7 of N channel enhancement mode transistor N2 are connected to node 1A, while the source 8 and the drain 32 of transistor N2 are connected to ground.
Discharge circuit 100-2 includes two parasitic diodes and an N channel enhancement mode transistor N3. The first parasitic diode D1, whose anode is connected to node 1A and whose cathode is connected to the power supply voltage V.sub.CC, represents the parasitic diode between the drain and the substrate of transistor P1. The second parasitic diode D2, whose anode is connected to ground and whose cathode is connected to the source of N channel transistor N3, represents the junction diode between source 10 and the substrate of N channel transistor N3. Drain 11 of transistor N3 is connected to power supply voltage V.sub.CC. Gate 9 and source 10 of transistor N3 are connected to node 1A.
The operation of a power-on reset circuit, similar to power-on reset circuit 100, is described in copending patent application Ser. No. 06/841,910 entitled "CMOS Power-on Reset Circuit", by John Mahoney, now U.S. Pat. No. 4,746,822, issued May 24, 1988, which is incorporated herein by reference. Briefly, the power-on reset signal is the output signal at node 1D of initializing buffer 100-5. This output signal assumes a first constant value as soon as the magnitude of the power supply voltage V.sub.CC rises above the level of the threshold voltage of transistor P3. The output signal of the initializing buffer 100-5 remains at the first constant value for a selected period of time sufficient to enable the components in the integrated circuit containing the power-on reset circuit 100 to stabilize. After the selected time period, the power-on reset circuit switches the output signal at node 1D to a second constant value.
The transistors N1 and P1 in delay circuit 100-1 do not conduct until the power supply voltage V.sub.CC has risen above the sum of the absolute value of the threshold voltages of transistors N1 and P1 which is a voltage level higher than the threshold voltage of transistor P3. The time required for the supply voltage to rise from the threshold voltage of transistor P3 to the level required to turn-on the transistors N1 and P1 constitutes one portion of the selected time period. A second portion of the selected time period is provided by the capacitance of transistor N2 in conjunction with the resistance provided by the transistors N1 and P1. This RC network also delays the rise of the voltage level on node 1A for a selected period of time. When the voltage on node 1A rises above the trigger point of inverter 100-3, the output signal of inverter 100-3 goes low, which in turn forces the output signal of the initializing buffer 100-5 to its second constant value.
The CMOS power-on reset circuit 100 in FIG. 1 is suitable for use with a power supply voltage that rises slowly (DC sweep), with a power supply voltage that rises to one-half of its maximum value in less than 100 nanoseconds, or with a power supply voltage having an intermediate rise time. The power-on reset circuit 100 does not respond to changes in the power supply voltage level after the reset signal is released, i.e., after the output signal of the initializing buffer 100-5 changes to its second constant value, and the circuit 100 maintains the second constant value output signal until the power supply voltage level drops to ground.
The response of circuit 100 to changes in the power supply voltage level after the circuit generates the second constant value output signal is shown in FIG. 2. The power supply voltage level V.sub.CC is plotted on the abscissa in FIG. 2, and the voltage at node 1A is plotted on the ordinate. The dotted line in FIG. 2 represents the variation of the trigger point of inverter 100-3 with the power supply voltage level V.sub.CC. The steady-state voltage at node 1A is the steady state power supply voltage level V.sub.CC, assumed to be +5 volts, minus the threshold voltage V.sub.T of transistor N1, assumed to be 1 volt. Accordingly, in FIG. 2, the steady-state voltage at node 1A is shown as 4 volts for a V.sub.CC of 5 volts.
As the power supply voltage level V.sub.CC decreases, the voltage at node 1A remains constant, as shown by the upper solid line in FIG. 2, because transistor N3 does not start to discharge the capacitor created using transistor N2 until the power supply voltage level falls to V.sub.CC minus 2 V.sub.T. Here, the threshold voltages V.sub.T of all N channel enhancement transistors in circuit 100 are assumed equal. As the power supply voltage level decreases from V.sub.CC minus 2 V.sub.T, transistor N.sub.3 turns on and discharges the capacitor so that the voltage at node 1A decreases linearly and continues to decrease to the value V.sub.T when the power supply voltage level reaches zero volts. During the linear decrease of the voltage at node 1A, the output signal at node 1D remains constant because the voltage at node 1A remains above the trigger point, represented by the dotted line in FIG. 2, of the inverter 100-3.
As the power supply voltage level increases from zero volts, the transistor N.sub.3 turns off and the capacitor will not start to charge until the power supply voltage is equal to twice the threshold voltage of N channel enhancement mode transistor. However, this assumes that the absolute value of the threshold voltage of transistor P.sub.1 is less than the threshold voltage of transistor N.sub.3. If the absolute value of the threshold voltage of transistor P1 is greater than the threshold voltage of transistor N3, the capacitor will not start to charge until the power supply voltage level is the sum of the absolute value of the threshold voltages of transistors N1 and P1. The increasing voltage at node 1A crosses the trigger point of the inverter 100-3, and the output signal of inverter 100-3 goes low, which in turn forces the output signal on node 1D of the initializing buffer 100-5 to its second constant value.
The hysteresis characteristic, illustrated in FIG. 2, of the power-on reset circuit 100 is desirable because the circuit 100 does not reset the components in the integrated circuit containing the power-on reset circuit 100 for minor power supply level variations. However, when the power supply voltage V.sub.CC drops below 3.5 to 4 volts, the operation of the memory components, flip-flops and similar components become unreliable. Consequently, the function of the integrated circuit is also unreliable when the power supply voltage level drops below 3.5 to 4 volts. The necessity of taking the power supply voltage V.sub.CC level all the way to ground, as required by the circuit of FIG. 1 and as shown in FIG. 2, to generate a reset signal, i.e. a signal which holds the integrated circuit containing the power-on reset circuit 100 in a known state, is undesirable. Accordingly, a means for generating a reset signal when the power supply voltage level falls below a selected value, but not all the way to zero, is desirable because the reset signal holds the integrated circuit in a known state until such time as the power supply voltage level returns to a level where the integrated circuit functions reliably.
Another prior art power-on reset circuit 101, shown in FIG. 3, uses a latch 120 to generate a reset signal when the power supply voltage is first supplied to the circuit, and also to generate a reset signal when the power supply voltage falls below a selected value, i.e., the threshold voltage of the field effect transistors in the power-on reset circuit 101. As shown in FIG. 3, power-on reset circuit 101 is comprised of a threshold detection circuit 160, a transient power supply voltage protection circuit 180, a latch 120, and a delay circuit 140. Latch 120 is a preferential cross-coupled latch of well known design and always powers up in the preferred state because of the geometries of the CMOS transistors comprising the latch 120.
The power-on reset circuit 101 generates a reset signal on the output terminal 141 when the power is initially applied to the integrated circuit which contains the power-on reset circuit 101. A reset signal is also generated whenever the power supply voltage level drops below the threshold voltage.
When power is initially applied to circuit 101, the power supply voltage level rises from 0 volts to 5 volts and as the power supply voltage level passes the threshold voltage, latch 120 activates in a known state. When latch 120 turns on, the output voltage signal V.sub.1 from latch 120 is transmitted to delay circuitry 140. After a time delay, the signal on the output terminal 141 is set to a first known state, which is a function of the voltage signal V.sub.1. The signal on output terminal 141 holds the remainder of the circuitry in the integrated circuit in a known power up state.
The integrated circuit containing circuit 101 is not rendered operational until the power supply voltage has reached approximately its nominal operating value. The threshold detection circuitry 160 resets latch 120 when the power supply voltage reaches a level greater than twice the threshold voltage. After latch 120 changes state, the signal on output terminal 141 changes to a second known state, complementary to the first known state, after a suitable delay determined by the delay circuit 140.
Latch 120 is designed so that the power-on reset circuitry will not generate another reset pulse unless the power supply voltage level drops below the threshold voltage. Thus, minor variations in the power supply voltage, which have no effect on proper operation of the integrated circuit, do not cause a reset pulse to be generated. When the power supply voltage level drops below the threshold voltage for only a short period, latch 120 may power up in a non-preferred state. This is prevented by the transient protection circuit 180. Transient protection circuitry 180 automatically drains off stored charge within latch 120 whenever the power supply voltage drops below the threshold voltage V.sub.T. This ensures that latch 120 powers up in the preferred state after a short transient.
While circuit 101 in FIG. 3 provides a means for resetting the components on an integrated circuit after a power supply voltage transient, the circuit has several undesirable features. The circuit does not generate a reset pulse until the power supply voltage level has fallen to the threshold voltage. As noted previously, most integrated circuits become unreliable when the power supply voltage level falls to the range of 3.5 to 4 volts which is considerably above the threshold voltage of a typical MOS transistor. Further, the function of the circuit 101 depends upon the specially designed latch 120, as shown in FIG. 3, and therefore this power-on reset circuit is not suitable for use with a power-on reset circuit such as that shown in FIG. 1. Accordingly, a means, which may be incorporated with any power-on reset circuit, is needed for sensing the power supply voltage level and generating a reset signal both when the power is first applied and when the power supply voltage level decreases below a selected value.